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HM-6642/883
Data Sheet March 2004 FN3013.2
512 x 8 CMOS PROM
The HM-6642/883 is a 512 x 8 CMOS NiCr fusible link Programmable Read Only Memory in the popular 24 pin, byte wide pinout. Synchronous circuit design techniques combine with CMOS processing to give this device high speed performance with very low power dissipation. On-chip address latches are provided, allowing easy interfacing with recent generation microprocessors that use multiplexed address/data bus structures, such as the 8085. The output enable controls, both active low and active high, further simplify microprocessor system interfacing by allowing output data bus control independent of the chip enable control. The data output latches allow the use of the HM-6642/883 in high speed pipelined architecture systems, and also in synchronous logic replacement functions. Applications for the HM-6642/883 CMOS PROM include low power hand held microprocessor based instrumentation and communications systems, remote data acquisition and processing systems, processor control store, and synchronous logic replacement. All bits are manufactured storing a logical "0" and can be selectively programmed for a logical "1" at any bit location.
Features
* This Circuit is Processed in Accordance to MIL-STD-883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1. * Low Power Standby and Operating Power - ICCSB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100A - ICCOP . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA at 1MHz * Fast Access Time. . . . . . . . . . . . . . . . . . . . . . . 120/200ns * Wide Operating . . . . . . . . . . . . . . . . . . . . -55C to +125C * Temperature Range * Industry Standard Pinout * Single 5.0V Supply * CMOS/TTL Compatible Inputs * Field Programmable * Synchronous Operation * On-Chip Address Latches * Separate Output Enable
Pin Description
PIN NC No Connect Address Inputs Chip Enable Data Output Power (+5V) Output Enable Program Enable P should be hardwired to GND except during programming. HM-6642/883 (CLCC) TOP VIEW
VCC NC A5 A6 A7 G1 26 25 24 23 22 21 20 19 12 Q1 13 Q2 14 GND 15 NC 16 Q3 17 Q4 18 Q5 G2 G3 E P NC Q7 Q6 A8 27
DESCRIPTION
Ordering Information
PKG. SBDIP SLIM SBDIP CLCC TEMP. RANGE (C) 120ns 200ns PKG. DWG. #
A0-A8 E Q VCC G1, G2, G3
-55 to +125 HM1-6642B/883 HM1-6642/883 D24.6 -55 to +125 HM6-6642B/883 HM6-6642/883 D24.3 -55 to +125 HM4-6642/883 J28.A
P (Note) NOTE:
Pinouts
M-6642/883 (SBDIP) TOP VIEW
A7 A6 A5 A4 A3 A2 A1 A0 Q0 Q1 Q2 GND 1 2 3 4 5 6 7 8 9 10 11 12 24 VCC 23 A8 22 G1 21 G2 20 G3 19 E 18 P 17 Q7 16 Q6 15 Q5 14 Q4 13 Q3 A4 A3 A2 A1 A0 NC Q0 5 6 7 8 9 10 11
4
3
2
1
28
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2004. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
HM-6642/883 Functional Diagram
A8 A7 A6 A5 A4 A3 LATCHED ADDRESS REGISTER
A 6 A 6 GATED ROW DECODER 64 x 64 MATRIX
64
ALL LINES POSITIVE LOGIC - ACTIVE HIGH THREE STATE BUFFERS: A HIGH OUTPUT ACTIVE 8 8 8 DATA LATCHES: L HIGH Q=D Q LATCHES ON RISING EDGE OF E ADDRESS LATCHES AND GATED DECODERS: LATCH ON FALLING EDGE OF E GATE ON FALLING EDGE OF E P SHOULD BE HARDWIRED TO GND EXCEPT DURING PROGRAMMING
8 A2 A1 A0 A LATCHED ADDRESS REGISTER 3 A 3 D E
8
8
8
8
GATED COLUMN DECODER
8-BIT DATA LATCH
G1 G2 G3 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
2
HM-6642/883
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V Input, Output or I/O Voltage . . . . . . . . . . . . GND-0.3V to VCC+0.3V Typical Derating Factor . . . . . . . . . . . 5mA/MHz Increase in ICCOP ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Information
Thermal Resistance (Typical) JA (C/W) JC (C/W) SBDIP Package . . . . . . . . . . . . . . . . . . 52 14 Slim SBDIP . . . . . . . . . . . . . . . . . . . . . 70 19 CLCC Package . . . . . . . . . . . . . . . . . . 58 14 Maximum Storage Temperature Range . . . . . . . . . .-65C to +150C Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +175C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300C
Operating Conditions
Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V Operating Temperature Range . . . . . . . . . . . . . . . .-55C to +125C Input Low Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +0.8V Input High Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 2.4 to VCC+0.3V
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1680 Gates
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
TABLE 1. HM-6642/883 DC ELECTRICAL PERFORMANCE SPECIFICATIONS Device Guaranteed and 100% Tested PARAMETER High Level Output Voltage Low Level Output Voltage High Impedance Output Leakage Current Input Leakage Current Standby Supply Current Operating Supply Current SYMBOL VOH VOL IIOZ II ICCSB ICCOP (NOTES 1, 4) CONDITIONS VCC = 4.5V, IO = -1.0mA VCC = 4.5V, IO = +3.2mA VCC = 5.5V, G = 5.5V, VI/O = GND or VCC VCC = 5.5V, VI = GND or VCC, P Not Tested VI = VCC or GND, VCC = 5.5V, IO = 0mA VCC = 5.5V, G = GND, G = VCC, (Note 3), f = 1MHz, IO = 0mA, VI = VCC or GND VCC = 4.5V (Note 5) GROUP A SUBGROUPS 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 TEMPERATURE (C) -55 TA +125 -55 TA +125 -55 TA +125 -55 TA +125 -55 TA +125 -55 TA +125 MIN 2.4 -1.0 -1.0 MAX 0.4 1.0 1.0 100 20 UNITS V V A A A mA
Functional Test
FT
7, 8A, 8B
-55 TA +125
-
-
-
TABLE 2. HM-6642/883 AC ELECTRICAL PERFORMANCE SPECIFICATIONS Device Guaranteed and 100% Tested (NOTES 1, 2, 4) CONDITIONS VCC = 4.5V and 5.5V VCC = 4.5V and 5.5V VCC = 4.5V and 5.5V VCC = 4.5V and 5.5V VCC = 4.5V and 5.5V VCC = 4.5V and 5.5V VCC = 4.5V and 5.5V VCC = 4.5V and 5.5V GROUP A SUBGROUPS 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 HM-6642B/883 TEMPERATURE (C) -55 TA +125 -55 TA +125 -55 TA +125 -55 TA +125 -55 TA +125 -55 TA +125 -55 TA +125 -55 TA +125 MIN 20 25 120 40 160 MAX 140 50 120 HM-6642/883 MIN 20 60 200 150 350 MAX 220 150 200 UNITS ns ns ns ns ns ns ns ns
PARAMETER Address Access Time Output Enable Access Time Chip Enable Access Time Address Setup Time Address Hold Time Chip Enable Low Width Chip Enable High Width Read Cycle Time NOTES:
SYMBOL TAVQV TGVQV TELQV TAVEL TELAX TELEH TEHEL TELEL
1. All voltages referenced to VSS. 2. A.C. measurements assume transition time < 5ns; input levels = 0.0V to 3.0V; timing reference levels = 1.5V; output load = 1TTL equivalent load and CL 50pF. 3. Typical derating = 5mA/MHz increase in ICCOP. 4. All tests performed with P hardwired to GND. 5. Tested as follows: f = 1MHz, VIH = 2.4V, VIL = 0.8V, IOH = -1mA, IOL = +1mA, VOH 1.5V, VOL 1.5V.
3
HM-6642/883
TABLE 3. APPLICABLE SUBGROUPS CONFORMANCE GROUPS Initial Test Interim Test PDA Final Test Group A Groups C & D METHOD 100%/5004 100%/5004 100%/5004 100%/5004 Samples/5005 Samples/5005 SUBGROUPS 1, 7, 9 1 2, 3, 7, 8A, 8B, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11 1, 7, 9
Switching Waveform
TAVQV TAVEL A TEHEL E TELQV TELAX ADD VALID TELEL TELEH TEHEL TAVEL NEXT ADD
Q TGXQZ
TGVQX TGVQV
DATA VALID TGXQZ
G (NOTE) TIME REFERENCE -1 0 1 2 3 456
NOTE: G has the same timing as G except signal is inverted. FIGURE 1. READ CYCLE
Test Load Circuit
DUT CL (NOTE) IOH NOTE: TEST HEAD CAPACITANCE, INCLUDES STRAY AND JIG CAPACITANCE
1.5V
IOL
EQUIVALENT CIRCUIT
FIGURE 2. TEST LOAD CIRCUIT
4
HM-6642/883 Burn-In Circuits
HM-6642/883 (0.300 INCH) SBDIP
VCC C F8 F7 F6 F5 F4 F3 F2 F1 2.4K 2.4K VCC/2 2.4K 1 2 3 4 5 6 7 8 9 A7 A6 A5 A4 A3 A2 A1 A0 Q0 VCC 24 A8 23 G1 22 G2 21 G3 20 E 19 P 18 Q7 17 Q6 16 Q5 15 Q4 14 Q3 13 F9 F10 F11 F12 F0 GND 2.4K 2.4K 2.4K 2.4K 2.4K VCC/2 F10 F9 F8 F7 F6 F5 F4 F3 1 2 3 4 5 6 7 8 9 VCC/2 A7 A6 A5 A4 A3 A2 A1 A0 Q0 VCC A8 G1 G2 G3 E P Q7 Q6 Q5 Q4 Q3 24 23 22 21 20 19 18 17 16 15 14 13 VCC/2 VCC F9 F10 F11 F12 F0 GND
HM-6642/883 (0.600 INCH) SBDIP
C
10 Q1 11 Q2 12 GND
10 Q1 11 Q2 12 GND
HM-6642/883 CLCC
VCC F10 25 24 23 22 21 NC 20 19 12 13 14 15 16 17 18 NC VCC 1.5K 1.5K 1.5K 1.5K 1.5K F6 F7 F8 F9
4 F5 F4 F3 F2 F1 5 6 7 8 9 NC 10 11
3
2
NC 28
C
1
27 26 F11 F12 F0
820 820 820 820 820 820 820 820 R2
NOTES: 1. F0 = 100kHz 10%. 2. All Resistors = 47k. 3. Unless Otherwise Noted. 4. VCC = 5.5V 0.5V. 5. VIL = 4.5V 10%. 6. C = 0.01F Min.
1.5K 1.5K 1.5K R1
5
HM-6642/883 Die Characteristics
DIE DIMENSIONS: 136 x 168 x 19 1mils METALLIZATION: Type: Si - Al Thickness: 11kA 15kA GLASSIVATION: Type: SiO2 Thickness: 8kA 1kA WORST CASE CURRENT DENSITY: 1.7 x 105 A/cm2
Metallization Mask Layout
HM-6642/883
A4 A5 A6 A7 VCC A8 G1 G2
A3 A2
G3 E
P
A1 A0 Q0 Q1 Q2 GND Q3 Q4 Q5 Q6 Q7
6
HM-6642/883 Ceramic Leadless Chip Carrier Packages (CLCC)
0.010 S E H S D D3
J28.A
MIL-STD-1835 CQCC1-N28 (C-4) 28 PAD CERAMIC LEADLESS CHIP CARRIER PACKAGE INCHES SYMBOL A A1 B B1 MIN 0.060 0.050 0.022 MAX 0.100 0.088 0.028 MILLIMETERS MIN 1.52 1.27 0.56 MAX 2.54 2.23 0.71 NOTES 6, 7 2, 4 2 2 2 5 5 3 3 3 Rev. 0 5/18/94
j x 45o
B
E3
E
B2 B3 D D1 D2
0.072 REF 0.006 0.442 0.022 0.460
1.83 REF 0.15 11.23 0.56 11.68
0.300 BSC 0.150 BSC 0.442 0.460 0.460 -
7.62 BSC 3.81 BSC 11.68 11.68
h x 45o 0.010 S E F S A A1 PLANE 2 PLANE 1
D3 E E1 E2 E3 e e1 h j
0.007 M E F S H S B1
11.23
0.300 BSC 0.150 BSC 0.460 -
7.62 BSC 3.81 BSC 11.68 1.27 BSC 0.38 1.02 REF 0.51 REF 1.14 1.14 1.90 0.08 7 7 28 1.40 1.40 2.41 0.038
0.050 BSC 0.015 -
-E-
0.040 REF 0.020 REF 0.045 0.045 0.075 0.003 7 7 28 0.055 0.055 0.095 0.015
L L1
L3
e
L -H-
L2 L3 ND NE N
-FE1 B3
NOTES: 1. Metallized castellations shall be connected to plane 1 terminals and extend toward plane 2 across at least two layers of ceramic or completely across all of the ceramic layers to make electrical connection with the optional plane 2 terminals. 2. Unless otherwise specified, a minimum clearance of 0.015 inch (0.38mm) shall be maintained between all metallized features (e.g., lid, castellations, terminals, thermal pads, etc.) 3. Symbol "N" is the maximum number of terminals. Symbols "ND" and "NE" are the number of terminals along the sides of length "D" and "E", respectively. 4. The required plane 1 terminals and optional plane 2 terminals (if used) shall be electrically connected. 5. The corner shape (square, notch, radius, etc.) may vary at the manufacturer's option, from that shown on the drawing. 6. Chip carriers shall be constructed of a minimum of two ceramic layers. 7. Dimension "A" controls the overall package thickness. The maximum "A" dimension is package height before being solder dipped. 8. Dimensioning and tolerancing per ANSI Y14.5M-1982. 9. Controlling dimension: INCH.
E2
L2 B2
L1
e1
D1
D2
7
HM-6642/883 Ceramic Dual-In-Line Metal Seal Packages (SBDIP)
c1 -A-DBASE METAL b1 M (b) SECTION A-A (c) LEAD FINISH
D24.3 MIL-STD-1835 CDIP4-T24 (D-9, CONFIGURATION C)
24 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE INCHES SYMBOL A b b1 b2 MIN 0.014 0.014 0.045 0.023 0.008 0.008 0.220 MAX 0.200 0.026 0.023 0.065 0.045 0.018 0.015 1.280 0.310 MILLIMETERS MIN 0.36 0.36 1.14 0.58 0.20 0.20 5.59 MAX 5.08 0.66 0.58 1.65 1.14 0.46 0.38 32.51 7.87 NOTES 2 3 4 2 3 5 6 7 2 8 Rev. 0 4/96
E M -Bbbb S C A - B S BASE PLANE SEATING PLANE S1 b2 b AA D S2 -CQ A L DS
b3 c c1 eA e eA/2
c
D E e eA eA/2 L Q S1 S2
0.100 BSC 0.300 BSC 0.150 BSC 0.125 0.015 0.005 0.005 90o 24 0.200 0.060 105o 0.015 0.030 0.010 0.0015
2.54 BSC 7.62 BSC 3.81 BSC 3.18 0.38 0.13 0.13 90o 24 5.08 1.52 105o 0.38 0.76 0.25 0.038
ccc M C A - B S D S
aaa M C A - B S D S
NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer's identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. Dimension Q shall be measured from the seating plane to the base plane. 6. Measure dimension S1 at all four corners. 7. Measure dimension S2 from the top of the ceramic body to the nearest metallization or lead. 8. N is the maximum number of terminal positions. 9. Braze fillets shall be concave. 10. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 11. Controlling dimension: INCH.
aaa bbb ccc M N
8
HM-6642/883 Ceramic Dual-In-Line Metal Seal Packages (SBDIP)
c1 -A-DBASE METAL b1 M (b) SECTION A-A (c) LEAD FINISH
D24.6 MIL-STD-1835 CDIP2-T24 (D-3, CONFIGURATION C)
24 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE INCHES SYMBOL A b b1 b2 MIN 0.014 0.014 0.045 0.023 0.008 0.008 0.500 MAX 0.225 0.026 0.023 0.065 0.045 0.018 0.015 1.290 0.610 MILLIMETERS MIN 0.36 0.36 1.14 0.58 0.20 0.20 12.70 MAX 5.72 0.66 0.58 1.65 1.14 0.46 0.38 32.77 15.49 NOTES 2 3 4 2 3 5 6 7 2 8 Rev. 0 4/94
E M -Bbbb S C A - B S BASE PLANE SEATING PLANE S1 b2 b AA D S2 -CQ A L DS
b3 c c1 eA e eA/2
c
D E e eA eA/2 L Q S1 S2
0.100 BSC 0.600 BSC 0.300 BSC 0.120 0.015 0.005 0.005 90o 24 0.200 0.075 105o 0.015 0.030 0.010 0.0015
2.54 BSC 15.24 BSC 7.62 BSC 3.05 0.38 0.13 0.13 90o 24 5.08 1.91 105o 0.38 0.76 0.25 0.038
ccc M C A - B S D S
aaa M C A - B S D S
NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer's identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. Dimension Q shall be measured from the seating plane to the base plane. 6. Measure dimension S1 at all four corners. 7. Measure dimension S2 from the top of the ceramic body to the nearest metallization or lead. 8. N is the maximum number of terminal positions. 9. Braze fillets shall be concave. 10. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 11. Controlling dimension: INCH.
aaa bbb ccc M N
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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